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1 cat25c01/02/04/08/16 1k/2k/4k/8k/16k spi serial cmos eeprom features 10 mhz spi compatible 1.8 to 6.0 volt operation hardware and software protection low power cmos technology spi modes (0,0 & 1,1)* commercial, industrial, automotive and extended temperature ranges 1,000,000 program/erase cycles 100 year data retention self-timed write cycle 8-pin dip/soic, 8/14-pin tssop and 8-pin msop 16/32-byte page write buffer block write protection C protect 1/4, 1/2 or all of eeprom array pin configuration dip package (p, l) pin functions pin name function so serial data output sck serial clock wp write protect v cc +1.8v to +6.0v power supply v ss ground cs chip select si serial data input hold suspends serial input nc no connect block diagram ? 2005 by catalyst semiconductor, inc. characteristics subject to change without notice description the cat25c01/02/04/08/16 is a 1k/2k/4k/8k/16k bit spi serial cmos eeprom internally organized as 128x8/256x8/512x8/1024x8/2048x8 bits. catalysts advanced cmos technology substantially reduces device power requirements. the cat25c01/02/04 features a 16-byte page write buffer. the 25c08/16 features a 32-byte page write buffer.the device operates via the spi bus serial interface and is enabled though a chip select ( cs ). in addition to the chip select, the clock input (sck), data in (si) and data out (so) are required to access the device. the hold pin may be used to suspend any serial communication without resetting the serial sequence. the cat25c01/02/04/08/16 is designed with software and hardware write protection features including block write protection. the device is available in 8-pin dip, 8-pin soic, 8-pin msop and 8/14-pin tssop packages. tssop package (u14, y14) sense amps shift registers spi control logic word address buffers i/o control e 2 prom array column decoders xdec high voltage/ timing control so 25c128 f02 status register block protect logic control logic data in storage si cs wp hold sck soic package (s, v) v ss so wp v cc hold sck si 1 2 3 4 8 7 6 5 cs so wp cs v cc sck si 1 2 3 4 8 7 6 5 v ss hold doc. no. 1016, rev. n tssop package (u, y) 8 7 6 5 v cc wp scl cs v ss 1 2 3 4 so hol d si so wp cs v cc sck si 1 2 3 4 8 7 6 5 v ss hold msop package (r, z)* *cat25c01/02 only h a l o g e n f r e e tm l e a d f r e e *other spi modes available on request. 14 13 12 11 10 9 8 v cc nc cs 1 2 3 4 5 6 7 so hold nc nc sck si nc nc nc wp v ss
2 cat25c01/02/04/08/16 doc. no. 1016, rev. n absolute maximum ratings* temperature under bias ................. C 55 c to +125 c storage temperature ....................... C 65 c to +150 c voltage on any pin with respect to v ss (1) .................. C 2.0v to +v cc +2.0v v cc with respect to v ss ................................ C 2.0v to +7.0v package power dissipation capability (ta = 25 c) ................................... 1.0w lead soldering temperature (10 secs) ............ 300 c output short circuit current (2) ........................ 100 ma *comment stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specifica- tion is not implied. exposure to any absolute maximum rating for extended periods may affect device perfor- mance and reliability. reliability characteristics symbol parameter min. max. units reference test method n end (3) endurance 1,000,000 cycles/byte mil-std-883, test method 1033 t dr (3) data retention 100 years mil-std-883, test method 1008 v zap (3) esd susceptibility 2000 volts mil-std-883, test method 3015 i lth (3)(4) latch-up 100 ma jedec standard 17 note: (1) the minimum dc input voltage is C 0.5v. during transitions, inputs may undershoot to C 2.0v for periods of less than 20 ns. maximum dc voltage on output pins is v cc +0.5v, which may overshoot to v cc +2.0v for periods of less than 20 ns. (2) output shorted for no more than one second. no more than one output shorted at a time. (3) this parameter is tested initially and after a design or process change that affects the parameter. (4) latch-up protection is provided for stresses up to 100 ma on address and data pins from C 1v to v cc +1v. (5) v ilmin and v ihmax are reference values only and are not tested. (6) maximum standby current (i sb ) = 10 a for the automotive and extended automotive temperature range. d.c. operating characteristics v cc = +1.8v to +6.0v, unless otherwise specified. limits symbol parameter min. typ. max. units test conditions i cc1 power supply current 5 ma v cc = 5v @ 5mhz (operating write) so=open; cs=vss i cc2 power supply current 3 ma v cc = 5.5v (operating read) f clk = 5mhz i sb (6) power supply current 1 a cs = v cc (standby) v in = v ss or v cc i li input leakage current 2 a i lo output leakage current 3 av out = 0v to v cc , cs = 0v v il (5) input low voltage -1 v cc x 0.3 v v ih (5) input high voltage v cc x 0.7 v cc + 0.5 v v ol1 output low voltage 0.4 v v oh1 output high voltage v cc - 0.8 v v ol2 output low voltage 0.2 v 1.8v v cc <2.7v v oh2 output high voltage v cc -0.2 v i ol = 150 a i oh = -100 a 2.7v v cc <5.5v i ol = 3.0ma i oh = -1.6ma
3 cat25c01/02/04/08/16 doc. no. 1016, rev. n limits 1.8v-6.0v 2.5v-6.0v 4.5v-5.5v test symbol parameter min. max. min. max. min. max. units conditions t su data setup time 50 20 20 ns v ih = 2.4v t h data hold time 50 20 20 ns c l = 100pf t wh sck high time 250 75 40 ns v ol = 0.8v t wl sck low time 250 75 40 ns v oh = 2.0v f sck clock frequency dc 1 dc 5 dc 10 mhz t lz hold to output low z 50 50 50 ns t ri (1) input rise time 2 2 2 s t fi (1) input fall time 2 2 2 s t hd hold setup time 100 40 40 ns t cd hold hold time 100 40 40 ns c l = 100pf t wc (3) write cycle time 10 5 5 ms t v output valid from clock low 250 75 40 ns t ho output hold time 0 0 0 ns t dis output disable time 250 75 75 ns t hz hold to output high z 150 50 50 ns t cs cs high time 500 100 100 ns t css cs setup time 500 100 100 ns t csh cs hold time 500 100 100 ns t wps wp setup time 150 50 50 ns t wph wp hold time 150 50 50 ns note: (1) this parameter is tested initially and after a design or process change that affects the parameter. (2) ac test conditions: input pulse voltages: 0.3v cc to 0.7v cc input rise and fall times: 10ns input and output reference voltages: 0.5v cc output load: current source iol max/ioh max; c l = 50pf (3) t wc is the time from the rising edge of cs after a valid write sequence to the end of the internal write cycle. a.c. characteristics c l = 50pf (2) pin capacitance (1) applicable over recommended operating range from t a =25 ? c, f=1.0 mhz, vcc=+5.0v (unless otherwise noted). symbol test conditions max. units conditions c out output capacitance (so) 8 pf v out =0v c in input capacitance ( cs , sck, si, wp , hold )6 pf v in =0v
4 cat25c01/02/04/08/16 doc. no. 1016, rev. n functional description the cat25c01/02/04/08/16 supports the spi bus data transmission protocol. the synchronous serial periph- eral interface (spi) helps the cat25c01/02/04/08/16 to interface directly with many of today s popular microcontrollers. the cat25c01/02/04/08/16 contains an 8-bit instruction register. (the instruction set and the operation codes are detailed in the instruction set table) after the device is selected with cs going low, the first byte will be received. the part is accessed via the si pin, with data being clocked in on the rising edge of sck. the first byte contains one of the six op-codes that define the operation to be performed. instruction opcode operation wren 0000 0110 enable write operations wrdi 0000 0100 disable write operations rdsr 0000 0101 read status register wrsr 0000 0001 write status register read 0000 x011 (1) read data from memory write 0000 x010 (1) write data to memory instruction set note: (1) x=0 for 25c01, 25c02, 25c08, 25c16. x=a8 for 25c04 (2) this parameter is tested initially and after a design or process change that affects the parameter. (3) t pur and t puw are the delays required from the time v cc is stable until the specified operation can be initiated. power-up timing (2)(3) symbol parameter max. units t pur power-up to read operation 1 ms t puw power-up to write operation 1 ms pin description si: serial input si is the serial data input pin. this pin is used to input all opcodes, byte addresses, and data to be written to the 25c01/02/04/08/16. input data is latched on the rising edge of the serial clock for spi modes (0, 0 & 1, 1). so: serial output so is the serial data output pin. this pin is used to transfer data out of the 25c01/02/04/08/16. during a read cycle, data is shifted out on the falling edge of the serial clock for spi modes (0,0 & 1,1). sck: serial clock sck is the serial clock pin. this pin is used to synchro- nize the communication between the microcontroller figure 1. sychronous data timing valid in v ih v il t css v ih v il v ih v il v oh v ol hi-z t su t h t wh t wl t v t cs t csh t ho t dis hi-z cs sck si so t ri t fi note: dashed line= mode (1, 1) C CCCC
5 cat25c01/02/04/08/16 doc. no. 1016, rev. n status register bits array address protection bp1 bp0 protected 0 0 none no protection 0 1 25c01: 60-7f quarter array protection 25c02: c0-ff 25c04: 180-1ff 25c08: 0300-03ff 25c16: 0600-07ff 1 0 25c01: 40-7f half array protection 25c02: 80-ff 25c04: 100-1ff 25c08: 0200-03ff 25c16: 0400-07ff 1 1 25c01: 00-7f full array protection 25c02: 00-ff 25c04: 000-1ff 25c08: 0000-03ff 25c16: 0000-07ff block protection bits 76543210 wpen 0 1 x bp1 bp0 wel rdy status register protected unprotected status wpen wp wp wp wp wp wel blocks blocks register 0 x 0 protected protected protected 0 x 1 protected writable writable 1 low 0 protected protected protected 1 low 1 protected writable protected x high 0 protected protected protected x high 1 protected writable writable write protect enable operation and the 25c01/02/04/08/16. opcodes, byte addresses, or data present on the si pin are latched on the rising edge of the sck. data on the so pin is updated on the falling edge of the sck for spi modes (0,0 & 1,1) . cs cs cs cs cs : chip select cs is the chip select pin. cs low enables the cat25c01/ 02/04/08/16 and cs high disables the cat25c01/02/ 04/08/16. cs high takes the so output pin to high impedance and forces the devices into a standby mode (unless an internal write operation is underway) the cat25c01/02/04/08/16 draws zero current in the standby mode. a high to low transition on cs is required prior to any sequence being initiated. a low to high transition on cs after a valid write sequence is what initiates an internal write cycle. byte address device address significant bits address don't care bits # address clock pulse cat25c01 a6 - a0 a7 8 cat25c02 a7 - a0 8 cat25c04 a7 - a0 (a8 = x bit from opcode) 8 cat25c08 a9 - a0 a15 - a10 16 cat25c16 a10 - a0 a15 - a11 16
6 cat25c01/02/04/08/16 doc. no. 1016, rev. n figure 2. wren instruction timing figure 3. wrdi instruction timing note: dashed line= mode (1, 1) C CCCC sk si cs so 00000 110 high impedance sk si cs so 00000 100 high impedance note: dashed line= mode (1, 1) C CCCC status register the status register indicates the status of the device. the rdy (ready) bit indicates whether the cat25c01/ 02/04/08/16 is busy with a write operation. when set to 1 a write cycle is in progress and when set to 0 the device indicates it is ready. this bit is read only. the wel (write enable) bit indicates the status of the write enable latch. when set to 1, the device is in a write enable state and when set to 0 the device is in a write disable state. the wel bit can only be set by the wren instruction and can be reset by the wrdi instruction. the bp0 and bp1 (block protect) bits indicate which blocks are currently protected. these bits are set by the user issuing the wrsr instruction. the user is allowed to protect quarter of the memory, half of the memory or the entire memory by setting these bits. once protected the user may only read from the protected portion of the array. these bits are non-volatile. the wpen (write protect enable) is an enable bit for the wp pin. the wp pin and wpen bit in the status register control the programmable hardware write pro- tect feature. hardware write protection is enabled when wp is low and wpen bit is set to high. the user cannot write to the status register, (including the block protect wp wp wp wp wp : write protect wp is the write protect pin. the write protect pin will allow normal read/write operations when held high. when wp is tied low and the wpen bit in the status register is set to 1 , all write operations to the status register are inhibited. wp going low while cs is still low will interrupt a write to the status register. if the internal write cycle has already been initiated, wp going low will have no effect on any write operation to the status register. the wp pin function is blocked when the wpen bit is set to 0. figure 10 illustrates the wp timing sequence during a write operation. hold hold hold hold hold : hold hold is the hold pin. the hold pin is used to pause transmission to the cat25c01/02/04/08/16 while in the middle of a serial sequence without having to re-transmit entire sequence at a later time. to pause, hold must be brought low while sck is low. the so pin is in a high impedance state during the time the part is paused, and transitions on the si pins will be ignored. to resume communication, hold is brought high, while sck is low. hold should be held high any time this function is not being used. hold may be tied high directly to v cc or tied to v cc through a resistor. figure 9 illustrates hold timing sequence.
7 cat25c01/02/04/08/16 doc. no. 1016, rev. n figure 4. read instruction timing note: dashed line= mode (1, 1) C C C C sk si so 0000x*01 1 byte address* 012345678910 2021222324252627282930 7 6 5 4 3 2 1 0 *please check the byte address table. cs opcode data out msb high impedance ** a n a 0 *x = 0 for cat25c01, cat25c02, cat25c08 and cat25c16; x = a8 for cat25c04 bits and the wpen bit) and the block protected sections in the memory array when the chip is hardware write protected. only the sections of the memory array that are not block protected can be written. hardware write protection is disabled when either wp pin is high or the wpen bit is zero. device operation write enable and disable the cat25c01/02/04/08/16 contains a write enable latch. this latch must be set before any write operation. the device powers up in a write disable state when v cc is applied. wren instruction will enable writes (set the latch) to the device. wrdi instruction will disable writes(reset the latch) to the device. disabling writes will protect the device against inadvertent writes. read sequence the part is selected by pulling cs low. the 8-bit read instruction is transmitted to the cat25c01/02/04/08/16, followed by the 16-bit address for 25c08/16. (only 10-bit addresses are used for 25c08, 11-bit addresses are used for 25c16. the rest of the bits are don't care bits) and 8-bit address for 25c01/02/04 (for the 25c04, bit 3 of the read data instruction contains address a8). after the correct read instruction and address are sent, the data stored in the memory at the selected address is shifted out on the so pin. the data stored in the memory at the next address can be read sequentially by continu- ing to provide clock pulses. the internal address pointer is automatically incremented to the next higher address after each byte of data is shifted out. when the highest address is reached, the address counter rolls over to 0000h allowing the read cycle to be continued indefi- nitely. the read operation is terminated by pulling the cs high. to read the status register, rdsr instruction should be sent. the contents of the status register are shifted out on the so line. the status register may be read at any time even during a write cycle. read sequece is illustrated in figure 4. reading status register is illustrated in figure 5. write sequence the cat25c01/02/04/08/16 powers up in a write dis- able state. prior to any write instructions, the wren instruction must be sent to cat25c01/02/04/08/16. the device goes into write enable state by pulling the cs low and then clocking the wren instruction into cat25c01/02/04/08/16. the cs must be brought high after the wren instruction to enable writes to the device. if the write operation is initiated immediately after the wren instruction without cs being brought high, the data will not be written to the array because the write enable latch will not have been properly set. also, for a successful write operation the address of the memory location(s) to be programmed must be outside the protected address field location selected by the block protection level.
8 cat25c01/02/04/08/16 doc. no. 1016, rev. n sk si so 00 00 x*0 10 d7 d6 d5 d4 d3 d2 d1 d0 012345678 2122232425262728293031 cs opcode data in high impedance byte address* ** a n a 0 *please check the byte address table x = 0 for cat25c01, cat25c02 and cat25c08, cat25c16; x = a8 for cat25c04. figure 6. write instruction timing byte write once the device is in a write enable state, the user may proceed with a write sequence by setting the cs low, issuing a write instruction via the si line, followed by the 16-bit address for 25c08/16. (only 10-bit addresses are used for 25c08, 11-bit addresses are used for 25c16. the rest of the bits are don't care bits) and 8-bit address for 25c01/02/04 (for the 25c04, bit 3 of the read data instruction contains address a8). programming will start after the cs is brought high. figure 6 illustrates byte write sequence. during an internal write cycle, all commands will be ignored except the rdsr (read status register) instruction. the status register can be read to determine if the write cycle is still in progress. if bit 0 of the status register is set at 1, write cycle is in progress. if bit 0 is set at 0, the device is ready for the next instruction page write the cat25c01/02/04/08/16 features page write capa- note: dashed line= mode (1, 1) C CCCC bility. after the initial byte, the host may continue to write up to 16 bytes of data to the cat25c01/02/04 and 32 bytes of data for 25c08/16. after each byte of data received, lower order address bits are internally incremented by one; the high order bits of address will remain constant.the only restriction is that the x (x=16 for 25c01/02/04 and x=32 for 25c08/16) bytes must reside on the same page. if the address counter reaches the end of the page and clock continues, the counter will roll over to the first address of the page and overwrite any data that may have been written. the cat25c01/02/04/08/16 is automatically returned to the write disable state at the completion of the write cycle. figure 8 illustrates the page write sequence. to write to the status register, the wrsr instruction should be sent. only bit 2, bit 3 and bit 7 of the status register can be written using the wrsr instruction. figure 7 illustrates the sequence of writing to status register. figure 5. rdsr instruction timing note: dashed line= mode (1, 1) C CCCC 012345678 10 911121314 sck si data out msb high impedance opcode so 7 6 5 4 3 2 1 0 cs 00 0 00 1 01
9 cat25c01/02/04/08/16 doc. no. 1016, rev. n figure 7. wrsr timing note: dashed line= mode (1, 1) C CCCC 012345678 10 911121314 sck si msb high impedance data in 15 so cs 7 6 5 4 3 2 10 00 0 000 0 1 opcode design considerations the cat25c01/02/04/08/16 powers up in a write disable state and in a low power standby mode. a wren instruction must be issued to perform any writes to the device after power up. also,on power up cs should be brought low to enter a ready state and receive an instruction. after a successful byte/page write or status register write, the cat25c01/02/04/08/ 16 goes into a write disable mode. cs must be set high after the proper number of clock cycles to start an internal write cycle. access to the array during an internal write cycle is ignored and programming is continued. on power up, so is in a high impedance. if an invalid op code is received, no data will be shifted into the cat25c01/02/04/08/16, and the serial output pin (so) will remain in a high impedance state until the falling edge of cs is detected again. when powering down, the supply should be taken down to 0v, so that the cat25c01/02/04/08/16 will be reset when power is ramped back up. if this is not possible, then, following a brown-out episode, the cat25c01/ 02/04/08/16 can be reset by refreshing the contents of the status register (see application note an10). figure 8. page write instruction timing note: dashed line= mode (1, 1) C CCCC sk si so 00 00 x*0 10 data byte 1 012345678 212223 24-31 32-39 data byte 2 data byte 3 data byte n cs opcode 7..1 0 24+(n-1)x8-1..24+(n-1)x8 24+nx8-1 data in high impedance byte address* *please check the byte address table. a n a 0 *x = 0 for cat25c01, cat25c02, cat25c08 and cat25c16; x = a8 for cat25c04.
10 cat25c01/02/04/08/16 doc. no. 1016, rev. n figure 10. wp wp wp wp wp timing note: dashed line= mode (1, 1) C CCCC t csh cs sck wp wp t wps t wph figure 9. hold hold hold hold hold timing cs sck hold so t cd t hd t hd t cd t lz t hz high impedance note: dashed line= mode (1, 1) C CCCC
11 cat25c01/02/04/08/16 doc. no. 1016, rev. n notes: (1) the device used in the above example is a 25c16si-1.8te13 (soic, industrial temperature, 1.8 volt to 6 volt operating volta ge, tape & reel) (2) cat25c01, cat25c02 only ordering information package p = 8-pin pdip r = 8-pin msop 2 s = 8-pin soic u = 8-pin tssop u14 = 14-pin tssop l = 8-pin pdip (lead free, halogen free) z = 8-pin msop 2 (lead free, halogen free) v = 8-pin soic, jedec (lead free, halogen free) y = 8-pin tssop (lead free, halogen free) y14 = 8-pin tssop (lead free, halogen free) prefix device # suffix 25c16 s i te13 product number 25c08: 8k 25c16: 16k 25c04: 4k 25c02: 2k 25c01: 1k tape & reel te13: 2000/reel operating voltage blank (v cc =2.5 to 6.0v) 1.8 (v cc =1.8 to 6.0v) -1.8 cat temperature range blank = commercial (0 c to +70 c) i = industrial (-40 c to +85 c) a = automotive (-40 c to +105 c) optional company id e = extended (-40 c to +125 c)
catalyst semiconductor, inc. corporate headquarters 1250 borregas avenue sunnyvale, ca 94089 phone: 408.542.1000 fax: 408.542.1200 www.catalyst-semiconductor.com publication #: 1016 revison: n issue date: 02/01/05 copyrights, trademarks and patents trademarks and registered trademarks of catalyst semiconductor include each of the following: dpp dpps ae 2 catalyst semiconductor has been issued u.s. and foreign patents and has patent applications pending that protect its products. for a complete list of patents issued to catalyst semiconductor contact the companys corporate office at 408.542.1000. catalyst semiconductor makes no warranty, representation or guarantee, express or implied, regarding the suitability of its products for any particular purpose, nor that the use of its products will not infringe its intellectual property rights or the rights of third parties with respect to any particular use or application and specifically disclaims any and all liability aris ing out of any such use or application, including but not limited to, consequential or incidental damages. catalyst semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgica l implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the catalyst semic onductor product could create a situation where personal injury or death may occur. catalyst semiconductor reserves the right to make changes to or discontinue any product or service described herein without not ice. products with data sheets labeled "advance information" or "preliminary" and other products described herein may not be in production or offered for sale . catalyst semiconductor advises customers to obtain the current version of the relevant product information before placing order s. circuit diagrams illustrate typical semiconductor applications and may not be complete. revision history date rev. reason 8/3/2004 m updated features updated dc operating characteristics table & notes 02/01/2005 n update ordering information

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